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MC100E310 5V ECL Low Voltage 2:8 Differential Fanout Buffer
Description
The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. The lowest TPD delay time results from terminating only one output pair, and the greatest TPD delay time results from terminating all the output pairs. This shift is about 10-20 pS in TPD. The skew between any two output pairs within a device is typically about 25 nS. If other output pairs are not terminated, the lowest TPD delay time results from both output pairs and the skew is typically 25 nS. When all outputs are terminated, the greatest TPD (delay time) occurs and all outputs display about the same 10 - 20 ps increase in TPD, so the relative skew between any two output pairs remains about 25 ns. For more information on using PECL, designers should refer to ON Semiconductor Application Note AN1406/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series Contains Temperature Compensation
Features
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PLCC-28 FN SUFFIX CASE 776
MARKING DIAGRAM*
1 28
MC100E310FNG AWLYYWW
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
* * * * * * * * * *
Dual Differential Fanout Buffers 200 ps Part-to-Part Skew 50 ps Output-to-Output Skew 28-lead PLCC Packaging Q Output will Default LOW with Inputs Open or at VEE PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; >2 kV, Machine Model; >200 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
* Moisture Sensitivity Level: Pb = 1; Pb-Free = 3 * * *
For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 212 devices Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 5
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Publication Order Number: MC100E310/D
MC100E310
Q0 25 VEE CLK_SEL CLKa VCC CLKa VBB CLKb 26 27 28 1 2 3 4 5 CLKb 6 NC 7 8 9 Q7 10 Q6 11 Q6 Pinout: 28-Lead PLCC (Top View) Q0 24 Q1 VCCO Q1 23 22 21 Q2 20 Q2 19 18 17 16 15 14 13 12 Q3 Q3 Q4 VCCO Q4 Q5 Q5 CLKa CLKa CLKb CLKb CLK_SEL Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 VCCO Q7 Q7 VBB * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout Assignment
Figure 2. Logic Symbol
Table 1. PIN DESCRIPTION
PIN CLKa, CLKb; CLKa, CLKb Q0:7; Q0:7 CLK_SEL VBB VCC, VCCO VEE NC Function ECL Differential Input Pairs ECL Differential Input Pairs ECL Differential Outputs ECL Input Clock Select Reference Voltage Output Positive Supply Negative Supply No Connect
Table 2. FUNCTION TABLE
PIN 0 1 Function CLKa Selected CLKb Selected
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Table 3. MAXIMUM RATINGS
Symbol VCC VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board PLCC-28 PLCC-28 PLCC-28 Condition 1 VEE = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 8 6 -6 50 100 0.5 0 to +85 -65 to +150 63.5 43.5 22 to 26 265 265 Unit V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC100E310
Table 4. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0 V (Note 1)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) Input HIGH Current Input LOW Current 0.5 0.3 3915 3170 3835 3190 3.62 2.7 Min Typ 55 3995 3305 3975 3355 Max 60 4120 3445 4120 3525 3.74 4.6 150 0.5 0.25 3975 3190 3835 3190 3.62 2.7 Min 25C Typ 55 4050 3255 3975 3355 Max 60 4120 3380 4120 3525 3.74 4.6 150 0.5 0.2 3975 3190 3835 3190 3.62 2.7 Min 85C Typ 65 4050 3260 3975 3355 Max 70 4120 3380 4120 3525 3.74 4.6 150 Unit mA mV mV mV mV V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 5. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0 V; VEE = -5.0 V (Note 4)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 5) Output LOW Voltage (Note 5) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) Input HIGH Current Input LOW Current 0.5 0.3 -1085 -1830 -1165 -1810 -1.38 -2.3 Min Typ 55 -1005 -1695 -1025 -1645 Max 60 -880 -1555 -880 -1475 -1.26 -0.4 150 0.5 0.25 -1025 -1810 -1165 -1810 -1.38 -2.3 Min 25C Typ 55 -950 -1745 -1025 -1645 Max 60 -880 -1620 -880 -1475 -1.26 -0.4 150 0.5 0.2 -1025 -1810 -1165 -1810 -1.38 -2.3 Min 85C Typ 65 -950 -1740 -1025 -1645 Max 70 -880 -1620 -880 -1475 -1.26 -0.4 150 Unit mA mV mV mV mV V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 5. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC100E310
Table 6. AC CHARACTERISTICS VCCx = 5.0 V; VEE= 0 V or VCCx = 0 V; VEE = -5.0 V (Note 7)
-40C Symbol fMAX tPLH tPHL tskew tJITTER VPP tr/tf Characteristic Maximum Toggle Frequency Propagation Delay to Output IN (differential) (Note 8) IN (single-ended) (Note 9) Within-Device Skew (Note 10) Part-to-Part Skew (Diff) Random Clock Jitter (RMS) Input Voltage Swing (Differential Configuration) Output Rise/Fall Time (20%-80%) 500 200 600 <1 500 200 600 Min 700 525 500 Typ 900 725 750 75 250 <1 500 200 600 Max Min 700 550 550 25C Typ 900 750 800 50 200 <1 Max Min 700 575 600 85C Typ 900 775 850 50 200 Max Unit MHz ps
ps ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. VEE can vary -0.46 V / +0.8 V. 8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12) of the ON Semiconductor High Performance ECL Data Book (DL140/D). 9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 10. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
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MC100E310
Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC100E310FN MC100E310FNG MC100E310FNR2 MC100E310FNR2G Package PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) Shipping 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100E310
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
B U
0.007 (0.180)
M
T L -M
M
S
N
S S
-N-
Y BRK D
0.007 (0.180)
T L -M
N
S
-L-
-M-
Z
W
V
D X VIEW D-D G1
0.010 (0.250)
S
T L -M
S
N
S
28
1
A
0.007 (0.180)
M M
T L -M T L -M
S S
N N
S S
Z
H
0.007 (0.180)
M
T L -M
S
N
S
R
0.007 (0.180)
C G G1
0.010 (0.250)
E
0.004 (0.100)
K1
J
-T-
SEATING PLANE
K F VIEW S
0.007 (0.180)
VIEW S
M
T L -M
S
N
S
S
T L -M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2 10 0.410 0.430 0.040
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 0.64 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 0.50 2 10 10.42 10.92 1.02
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MC100E310
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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MC100E310/D

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